Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.

TECHNICAL FIELD

The present invention relates to a semiconductor device, and morespecifically, a semiconductor device in which a main current flows in adirection of the thickness of a semiconductor substrate.

BACKGROUND ART

As an example of a semiconductor device in which a main current flows ina direction of the thickness of a semiconductor substrate, a structureis suggested where an IGBT (insulated gate bipolar transistor) elementand a diode element in parallel connection with the IGBT element areadjacently formed.

For example, Japanese Patent Application Laid-Open No. 11-097715discloses an example where gate electrode structures are formed on afirst main surface side of a semiconductor substrate, P type impurityregions and N type impurity regions are alternately and adjacentlyformed in a surface of a second main surface, the P type impurityregions and the gate electrode structures constitute an IGBT region, andthe N type impurity regions and the gate electrode structures constitutea diode region.

In such a structure, since the P type impurity regions and the N typeimpurity regions on the second main surface side are in contact witheach other, for example, a phenomenon called snapback occurs, resultingin a loss of energy in a switching operation of an IGBT element, therebyleading to an inability to obtain desirable electric characteristics.

DISCLOSURE OF INVENTION

An object of the present invention is to provide a semiconductor devicein which a main current flows in a direction of the thickness of asemiconductor substrate that enables to attain desirable electriccharacteristics when semiconductor elements with a different functionare adjacently arranged.

A semiconductor according to the present invention includes a first mainelectrode provided on a first main surface of a semiconductor substrate,a second main electrode provided on a second main surface of thesemiconductor substrate, and at least one trench-type gate electrodeprovided in a surface of the first main surface. A main current flows ina direction of the thickness of the semiconductor substrate. Thesemiconductor substrate includes at least one trench isolation structureprovided in a surface of the second main surface, and a first impurityregion of a first conductivity type and a second impurity region of asecond conductivity type provided in a surface of the second mainsurface. At least one trench isolation structure is formed by filling atrench provided in a surface of the second main surface with aninsulator or a semiconductor of a conductivity type reverse to that ofthe semiconductor substrate. The trench isolation structure is providedso as to separate the first impurity region and the second impurityregion.

The semiconductor device of the present invention is applicable, forexample, in a case where the first impurity region is used as a drainregion of a MOSFET element and a cathode region of a diode element andthe second impurity region is used as a collector region of an IGBTelement. In this case, the presence of at least one trench isolationstructure causes a resistance value of a current path during an IGBTelement operation to increase and a current that flows through thecurrent path upon modulation to decrease. Therefore, snapback can besuppressed. Further, by providing at least one trench isolationstructure, snapback can be suppressed without reducing the proportion ofan area of an effective region (the sum of areas of the first impurityregion and the second impurity region) in the second main surface.Therefore, an increase of an ON voltage during an IGBT element operationand a forward voltage Vf during a diode element operation as well as anincrease of a local current density during respective operations can beprevented.

The present invention is intended for a manufacturing method of asemiconductor device including a first main electrode provided on afirst main surface of a semiconductor substrate, a second main electrodeprovided on a second main surface of the semiconductor substrate, and atleast one trench-type gate electrode provided in a surface of the firstmain surface, wherein a main current flows in a direction of thethickness of the semiconductor substrate. According to the presentinvention, the method includes the following steps of (a) through (c).The step (a) is to form at least one trench in a surface of the secondmain surface after forming the structure on the side of the first mainsurface in a semiconductor wafer state. The step (b) is to form in thesemiconductor wafer state an insulator layer or a semiconductor layer ofa conductivity type reverse to that of the semiconductor substrateentirely on the second main surface to fill the insulator layer or thesemiconductor layer inside at least one trench. The step (c) is toremove the insulator layer or the semiconductor layer on the second mainsurface to obtain at least one trench isolation structure.

According to the manufacturing method of the semiconductor device of thepresent invention, at least one trench isolation structure provides, forexample, a configuration where an impurity region functioning as a drainregion of a MOSFET element and a cathode region of a diode element isseparated from an impurity region functioning as a collector region ofan IGBT element. Under this configuration, the presence of at least onetrench isolation structure causes a resistance value of a current pathduring a MOSFET element operation to increase and a current that flowsthrough the current path upon modulation to decrease. Therefore,snapback can be suppressed. Further, by providing at least one trenchisolation structure, snapback can be suppressed without reducing theproportion of an area of an effective region (the sum of areas of thefirst impurity region and the second impurity region) in the second mainsurface. Therefore, an increase of an ON voltage during an IGBT elementoperation and a forward voltage Vf during a diode element operation aswell as an increase of a local current density during respectiveoperations can be prevented.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a section view showing a structure of a semiconductor devicefor explaining developments of the present invention.

FIG. 2 shows an equivalent circuit illustrating an operation of thesemiconductor device for explaining developments of the presentinvention.

FIG. 3 shows an operating characteristic of the semiconductor device forexplaining developments of the present invention.

FIG. 4 is a section view showing a structure of a semiconductor deviceaccording to an embodiment of the present invention.

FIG. 5 illustrates an example of a plane structure of the semiconductordevice according to the embodiment of the present invention.

FIG. 6 illustrates an example of a plane structure of the semiconductordeice according to the embodiment of the present invention.

FIG. 7 illustrates an example of a plane structure of the semiconductordevice according to the embodiment of the present invention.

FIG. 8 illustrates an example of a plane structure of the semiconductordevice according to the embodiment of the present invention.

FIG. 9 illustrates an example of a plane structure of the semiconductordevice according to the embodiment of the present invention.

FIG. 10 illustrates an example of a plane structure of the semiconductordevice according to the embodiment of the present invention.

FIG. 11 illustrates an example of a plane structure of the semiconductordevice according to the embodiment of the present invention.

FIG. 12 is a plane view illustrating a structure of the semiconductorsubstrate wafer employed in a semiconductor device of the presentinvention.

FIG. 13 shows an equivalent circuit illustrating an operation of thesemiconductor device according to the embodiment of the presentinvention.

FIG. 14 illustrates an operating characteristic of the semiconductordevice according to the embodiment of the present invention.

FIG. 15 is a section view illustrating a manufacturing step of thesemiconductor device according to the embodiment of the presentinvention.

FIG. 16 is a section view illustrating a manufacturing step of thesemiconductor device according to the embodiment of the presentinvention.

FIG. 17 is a section view illustrating a manufacturing step of thesemiconductor device according to the embodiment of the presentinvention.

FIG. 18 is a section view illustrating a manufacturing step of thesemiconductor device according to the embodiment of the presentinvention.

FIG. 19 is a section view illustrating a structure of a variation of thesemiconductor device according to the embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

Prior to describing an embodiment according to the present invention,description is given as to how the technical idea of the presentinvention has been developed with reference to FIGS. 1 through 3.

FIG. 1 is a section view illustrating a basic structure of asemiconductor device 90 intended to solve the problem with theconventional semiconductor device.

In the configuration of the semiconductor device 90 shown in FIG. 1, a Ptype semiconductor region 902 is formed entirely across in a surface ofa first main surface MS1 of a semiconductor substrate 901 that is an Ntype substrate having a high specific resistance (N⁻).

Then, two trenches 903 are provided penetrating the P type semiconductorregion 902 from the first main surface MS1 and reaching inside thesemiconductor substrate 901. Inner walls of trenches 903 are coveredwith gate insulating films 904. Further, conductive materials fillinside trenches 903 covered with the gate insulating films 904 to formtrench-type gate electrodes 905.

Also, N type semiconductor regions 906 of a relatively highconcentration (N⁺) are selectively formed in the surface of the P typesemiconductor region 902 so that at least a part of the N typesemiconductor regions 906 comes in contact with the gate insulatingfilms 904. The N type semiconductor regions 906 are provided on bothsides of each of the two trenches 903. P type semiconductor regions 907of a relatively high concentration (P⁺) are formed between a pair of theN type semiconductor regions 906 sandwiched by the trenches. The P typesemiconductor regions 907 provide a structure for obtaining a preferableelectric contact for the P type semiconductor region 902.

Further, first main electrodes 908 are provided in contact with the topof the N type semiconductor regions 906 and the P type semiconductorregions 907 adjacent to each other.

The first main electrodes 908 apply a potential from an externalterminal ET to the N type semiconductor regions 906 and the P typesemiconductor regions 907. In response to an operation of thesemiconductor device 90, at some time the first main electrodes 908function as an emitter electrode and at other times they function as ananode electrode or a source electrode. Further, a control voltage isapplied from an external terminal GT to the trench-type gate electrodes905.

P type semiconductor regions 912 and N type semiconductor regions 913are alternately provided with an interval therebetween, both regions ina surface of a second main surface MS2 of the semiconductor substrate901. Further, a second main electrode 916 is provided contacting boththe P type semiconductor regions 912 and the N type semiconductorregions 913.

With the P type semiconductor regions 912 and the N type semiconductorregions 913 arranged apart, this structure is intended to improveelectric characteristics.

The second main electrode 916 applies a potential from an externalterminal CT to the P type semiconductor regions 912 and the N typesemiconductor regions 913. At some time the second main electrode 916functions as a collector electrode, and at other times it functions as acathode electrode or a drain electrode.

Next, description is given of an operation of the semiconductor device90 in reference to FIGS. 2 and 3. FIG. 2 shows an equivalent circuitschematically illustrating function of the semiconductor device 90. FIG.2 shows that the semiconductor device 90 functions as an IGBT elementand a diode element in an inverse-parallel connection with the IGBTelement. Further, FIG. 3 shows current-voltage characteristics of thesemiconductor device 90.

FIG. 2 shows that the P type semiconductor region 912 and the N typesemiconductor region 913 are provided in a surface of the second mainsurface MS2 with an interval therebetween. Under this configuration,when a ground potential is supplied to the external terminal ET, apositive potential is supplied to the external terminal CT and an ONsignal is supplied to the external terminal GT, a current path (1) and acurrent path (2) are formed leading to the first main surface MS1 side.The current path (1) starts from the N type semiconductor region 913,goes through a path having resistors R1 and R2 inside the semiconductorsubstrate 901 and a channel region formed inside the P typesemiconductor region 902 in contact with the gate insulating film 904,and reaches the N type semiconductor region 906. The current path (2)starts from the P type semiconductor region 912, goes through a pathhaving the resistor R2 inside the semiconductor substrate 901 and thechannel region formed inside the P type semiconductor region 902 incontact with the gate insulating film 904, and reaches the N typesemiconductor region 906.

In this case, the current path (1) is taken during an operation as aso-called MOSFET element, and the current path (2) is taken during anoperation as a so-called IGBT element.

Further, when a ground potential is supplied to the external terminalET, a negative potential is supplied to the external terminal CT and anOFF signal is supplied to the external terminal GT, the semiconductordevice 90 functions as a diode element. Therefore, a current flowsthrough the N type semiconductor region 913 via a path having a resistorR3 inside the semiconductor substrate 901.

If a portion inside the semiconductor substrate 901 near the P typesemiconductor region 912 is called an X, a resistance value of theresistor R1 between the X and the N type semiconductor region 913 isvery small when the N type semiconductor region 913 and the P typesemiconductor region 912 are close.

Additionally in FIG. 2, regarding the resistors R2 and R3 inside thesemiconductor substrate 901 during an IGBT element operation and a diodeelement operation, respectively, modulation is generated and aresistance value decreases as a voltage increases. Accordingly, a symbolindicating a variable resistor is used for the resistors R2 and R3.However, in case of a MOSFET element operation, the resistance value isapproximately constant.

FIG. 3 conceptually shows current-voltage characteristics of thesemiconductor device 90. That is, in FIG. 3, the horizontal axisrepresents voltage value and the vertical axis represents current value,to indicate four kinds of current-voltage characteristics that arecharacteristics A, B, C and D.

The characteristic A shows the relationship of a current flowing at theexternal terminal CT and a potential difference between the externalterminal CT and the X when the N type semiconductor region 913 is in anopen state without being connected to the external terminal CT.

The characteristic B shows the relationship of a current flowing at theexternal terminal CT and a potential difference between the externalterminal CT and the X when the P type semiconductor region 912 is in anopen state without being connected to the external terminal CT.

The characteristic C shows the relationship of a current flowing at theexternal terminal CT and the potential difference between the externalterminal CT and the external terminal ET when the N type semiconductorregion 913 is in an open state without being connected to the externalterminal CT.

The characteristic D shows the relationship of a current flowing at theexternal terminal CT and the potential difference between the externalterminal CT and the external terminal ET when the P type semiconductorregion 912 is in an open state without being connected to the externalterminal CT.

The characteristic B is a straight line with a slope of 1/R1, and thecharacteristic A indicates that almost no current flows before apotential difference between the external terminal CT and the X reachesapproximately 0.6V.

Next, description is given of a case when the N type semiconductorregion 913 and the P type semiconductor region 912 are both connected tothe external terminal CT.

When the current level is low, the potential difference between theexternal terminal CT and the X is small and the IGBT element does notoperate. Therefore, mainly the MOSFET element operates and a currentflows virtually through the current path (1).

Then, when modulation is generated, the IGBT element operates and acurrent starts to flow, that is, when a potential difference between theexternal terminal CT and the X reaches about 0.6V, the characteristic Dtakes a current value and a voltage value as represented by a Z.

Hereinafter, a voltage when the IGBT element operation prompts a currentto flow, that is, a voltage when modulation starts to be generated, isdefined as a modulation voltage Vmod.

Further, when an attempt is made to supply a current over the levelindicated by the Z, the IGBT element operation through the current path(2) gradually takes over. Since the amount of a current prompted by theIGBT element operation increases exponentially while the amount of acurrent prompted by the MOSFET element operation increases onlylinearly, when a current over the level indicated by the Z is supplied,a phenomenon where a potential difference between the external terminalCT and the external terminal ET decreases, namely, a snapbackphenomenon, is observed.

FIG. 3 shows a characteristic E indicating that a current increasessharply as a voltage decreases with the Z on the characteristic D as aturn-round. This characteristic corresponds to a snapback phenomenon.

Additionally, a negative resistance region where a snapback phenomenonis observed is referred to as a snapback region.

Observing a switching operation with passage of time, when a snapbackphenomenon occurs, a period of time arises when both a current and avoltage increase. This leads to a loss of energy.

As described above, even under a configuration where the P typesemiconductor region 912 and the N type semiconductor region 913 areprovided without contacting each other, a snapback phenomenon occurs ifboth regions are close. By further increasing the interval between the Ntype semiconductor region 913 and the P type semiconductor region 912, aproportion of an area of an effective region (the sum of areas of the Ptype semiconductor region 912 and the N type semiconductor region 913)in the second main surface MS2 decreases. This shifts thecharacteristics A and C slightly to the higher voltage side (to theright of FIG. 3).

Further, an increased interval between the P type semiconductor region912 and the N type semiconductor region 913 causes the resistance valueof the resistor R1 (FIG. 2) to increase. This lessens the slope of thecharacteristic B.

Furthermore, in case the interval between the P type semiconductorregion 912 and the N type semiconductor region 913 is widened but thearea of a semiconductor chip is not increased, naturally the area of theN type semiconductor region 913 decreases and the area of the N typesemiconductor region 913 in proportion to the semiconductor chipdecreases. As a result, the characteristic D shows a slightly lowerslope.

Moreover, an increased value of the resistor R1 between the P typesemiconductor region 912 and the N type semiconductor region 913 lessensthe slope of the characteristic B. Therefore, even when a potentialdifference between the external terminal CT and the X reaches about 0.6V, a current flow prompted by the MOSFET element operation is not solarge and a potential difference between the external terminal CT andthe external terminal ET is small, thereby suppressing snapback. Here,when a potential difference between the external terminal CT and the Xreaches about 0.6 V, that is, at the Z, the following relationshipholds: Vmod=R1×id. The id refers to an operating current of the MOSFETelement, that is, a current flowing through the current path (1). Inthis case, it particularly refers to a current value at the Z.

However, as mentioned above, an increased interval between the P typesemiconductor region 912 and the N type semiconductor region 913decreases the proportion of an area of an effective region in the secondmain surface MS2. This increases an ON voltage during the IGBT elementoperation and a forward voltage Vf during the diode element operation,or increases a local current density during respective operations.

The snapback can also be suppressed by decreasing the area of the N typesemiconductor region 913 in proportion to the P type semiconductorregion 912. Therefore, if the area of the N type semiconductor region913 is made extremely small in proportion to the P type semiconductorregion 912, it is possible to make snapback unobservable. However,decreased area of the N type semiconductor region 913 causes a forwardvoltage Vf to increase during a diode element operation, or a currentdensity to increase to a very large extent that a diode element may bedamaged.

In this regard, the inventors of the present application reached atechnical idea that a trench is provided in the surface of thesemiconductor substrate 901 between the N type semiconductor region 913and the P type semiconductor region 912. In the following, as theembodiment according to the present invention, description is given ofstructure and operation of a semiconductor device 100 created based onthe above technical concept.

A. Device Structure

-   -   A-1. Sectional Structure

FIG. 4 is a section view showing a basic structure of the semiconductordevice 100.

The semiconductor device 100 shown in FIG. 4 is so configured that the Ptype semiconductor region 902 is formed entirely across in a surface ofthe first main surface MS1 of the semiconductor substrate 901 that is anN type substrate having a high specific resistance (N⁻). Depending on awithstand voltage level, a specific resistance and a distance L betweenthe bottom of the P type semiconductor regions 912 and the bottom of thetrenches 903 of the semiconductor substrate 901 vary. For example, at awithstand voltage level of 1200V, the specific resistance is set to 40to 60 Ωcm and the distance L is set to about 100 to 200 μm. For lowerwithstand voltage levels, the specific resistance is set to a lowervalue and the distance L is set to a smaller value.

Then, two trenches 903 are provided penetrating the P type semiconductorregion 902 from the first main surface MS1 and reaching inside thesemiconductor substrate 901. Inner walls of the trenches 903 are coveredwith gate insulating films 904. Further, conductive materials fillinside the trenches 903 covered with the gate insulating films 904 toform trench-type gate electrodes 905.

When the semiconductor device 100 functions as a MOSFET element or anIGBT element, the P type semiconductor region 902 serves as a bodyregion including a channel region. Therefore, an impurity concentrationand a depth of the P type semiconductor region 902 are determined basedon a threshold voltage of the MOSFET or the IGBT.

The impurity concentration and a diffusion depth are determined by anion implantation condition or a thermal diffusion condition. Forexample, the impurity concentration is usually set to be 1×10¹⁷atoms/cm³ to 1×10¹⁸ atoms/cm³ in an area contacting a source electrodeof the MOSFET or an emitter electrode of the IGBT. The diffusion depthis set to be several μms so as not to exceed the trenches 903.

Further, respective trenches 903 are formed by etching at pitch of 2 to10 μm, with a width set between 0.5 to 3.0 μm and a depth set between 3to 20 μm.

The gate insulating films 904 formed on the surface of the inner wall ofthe trenches 903 are insulating films constituting the MOSFET, and havean optimum thickness specified based on a gate drive voltage, asaturated current, a capacitance and the like. Generally, a siliconoxide film with a thickness of 10 to 200 nm is used to form the gateinsulating films 904 by thermal oxidation, deposition and the like.

The trench-type gate electrodes 905 filled inside the trenches 903comprise a polycrystalline silicon film of a high impurityconcentration, a metal material with a high melting point such astungsten silicide and the like, or a multilayered film structure ofthese. Generally, the trench-type gate electrodes 905 are obtained bydepositing a conductive film thicker than half the width of the trenches903 over the first main surface MS1 then planarizing the film byanisotropic etching and the like. Also, the trench-type gate electrodes905 are obtained by forming a mask with a predetermined pattern by photolithography then depositing a conductive film and performing etching.

An optimal concentration of the P type semiconductor region 902 variesdepending on a work function value of a material of the trench-type gateelectrodes 905. In an extreme case, an N type semiconductor region isprovided along the side of the trenches 903 and a thin layer having thesame conductivity type as that of an emitter region (N type) is providedin a region contacting the gate insulating films 904, thereby forming aburied channel structure.

Also, the N type semiconductor regions 906 of a relatively highconcentration (N⁺) are selectively formed in the surface of the P typesemiconductor region 902 so that at least a part of the N typesemiconductor regions 906 comes in contact with the gate insulatingfilms 904. The N type semiconductor regions 906 are provided on bothsides of each of the two trenches 903. The P type semiconductor regions907 of a relatively high concentration (P⁺) are formed between a pair ofthe N type semiconductor regions 906 sandwiched by the trenches. The Ptype semiconductor regions 907 provide a structure for obtaining apreferable electric contact for the P type semiconductor region 902.

The N type semiconductor regions 906 and the P type semiconductorregions 907 are both formed through patterning by photo lithography andion implantation so as to have a surface concentration of over 1×10²⁰atoms/cm³, for example.

Further, the first main electrodes 908 are provided in contact with thetop of the N type semiconductor regions 906 and the P type semiconductorregions 907 adjacent to each other.

The first main electrodes 908 apply a potential from the externalterminal ET to the N type semiconductor regions 906 and the P typesemiconductor regions 907. In response to an operation of thesemiconductor device 90, at some time the first main electrodes 908function as an emitter electrode and at other times they function as ananode electrode or a source electrode. Further, a control voltage isapplied from the external terminal GT to the trench-type gate electrodes905.

The first main electrodes 908 are formed by processing an interlayerinsulating film (not shown) formed so as to cover the N typesemiconductor regions 906 and the P type semiconductor regions 907 byphoto lithography and etching to selectively create an opening, thendepositing a conductive film comprising a compound of aluminum andsilicon, for example.

Further, a protective film (not shown) is formed on the first mainelectrodes 908, and a connection to an external power source is madethrough an opening portion provided at a predetermined position of theprotective film.

The P type semiconductor regions 912 and the N type semiconductorregions 913 are alternately provided with an interval therebetween, bothregions in the second main surface MS2 of the semiconductor substrate901. Between the P type semiconductor regions 912 and the N typesemiconductor regions 913, trenches in the surface of the semiconductorsubstrate 901 are filled with insulators 914, thereby forming trenchisolation structures 911.

An impurity concentration of the P type semiconductor regions 912 andthe N type semiconductor regions 913 is both from 1×10¹⁶ atoms/cm³ to1×10²¹ atoms/cm³. For example, the regions are formed through ionimplantation to implant a predetermined impurity, then annealing foractivation. However, depending on a property of a semiconductor device,in some cases an impurity concentration outside the above-mentionedrange is acceptable and in some other cases annealing is not required.

Further, the second main electrode 916 is provided contacting both the Ptype semiconductor regions 912 and the N type semiconductor regions 913.It is noted that the trench isolation structures 911 are provided in asurface of the second main surface MS2 so that an exposed surface of thetrench isolation structures 911 is level with an exposed surface of theP type semiconductor regions 912 and the N type semiconductor regions913. Further, the second main electrode 916 is provided so as to coverthe top of the trench isolation structures 911.

The second main electrode 916 applies a potential from the externalterminal CT to the P type semiconductor regions 912 and the N typesemiconductor regions 913. At some time the second main electrode 916functions as a collector electrode, and at other times it functions as acathode electrode or a drain electrode.

The trench isolation structures 911 are formed by anisotropic etchingand the like, to have an optimum depth determined based on a specificresistance of the semiconductor substrate 901, an impurity concentrationof the N type semiconductor regions 913 and the P type semiconductorregions 912, an area ratio of both regions, a material of the insulators914 constituting the trench isolation structures 911, and throughput.

Further, any value can be given for the a width and an arrangementinterval of the trench isolation structures 911. For example, the widthis set to 0.2 to 100 μm and the arrangement interval is set to 0.5 to500 μm.

A material and a size for the insulators 914 constituting the trenchisolation structures 911 are decided so that an electrical chargetherein has a polarity reverse to an electrical charge inside thesemiconductor substrate 901 and that the total quantity of theelectrical charge of all the trench isolation structures 911 isapproximately equal to the quantity of the electrical charge of asection of the semiconductor substrate 901 from the surface of thesecond main surface MS2 to the bottom of the trench isolation structures911. For example, assuming that an N type impurity concentration of thesemiconductor substrate 901 is n (atoms/cm³), a width, a depth and athickness of the trench isolation structures 911 are W, t and x,respectively, the distance between centerlines of the trench isolationstructures 911 (trench arrangement pitch) is P, and an elementaryquantity of electricity is q, then a section of the semiconductorsubstrate 901 sandwiched by two trench isolation structures 911 has anegative electrical charge of qn·(P−W)tx. Therefore, a material of theinsulators 914 is decided so that a positive electrical charge equal inquantity to the above negative electrical charge is present inside eachof the trench isolation structures 911. More specifically, an insulatorhaving a constant electrical charge density of n·(P−W)/W is used.

Set in this manner, a Reduced Surface Field (RESURF) effect allows awithstand voltage level to increase with stability, thereby making itpossible to reduce the thickness of the semiconductor substrate 901.Further, since a concentration of the semiconductor substrate 901 can beincreased, it is possible to lower an ON voltage for an IGBT element anda forward voltage Vf for a diode element, thereby alleviating a loss ofenergy.

When the semiconductor device 100 operates as an IGBT element, the firstmain electrodes 908 function as an emitter electrode, the second mainelectrode 916 functions as a collector electrode, and the N typesemiconductor regions 906 formed in the first main surface MS1 functionas an emitter region. Further, the P type semiconductor region 902functions as a body region including a channel region and the P typesemiconductor regions 907 function as a body contact region.

Moreover, when operating as a diode element, the first main electrodes908 function as an anode electrode, the second main electrode 916functions as a cathode electrode, and the P type semiconductor region902 formed in the first main surface MS1 functions as an anode region.Further, the P type semiconductor regions 907 function as an anodecontact region and the N type semiconductor regions 913 formed on theside of the second main surface MS2 functions as a cathode region.

Furthermore, when operating as a MOSFET element, the first mainelectrodes 908 function as a source electrode, the second main electrode916 functions as a drain electrode, and the N type semiconductor regions906 function as a source region. Further, the P type semiconductorregion 902 functions as a body region including a channel region, the Ptype semiconductor regions 907 function as a body contact region, andthe N type semiconductor regions 913 function as a drain region.

-   -   A-2. Planar Structure

Next, description is given of a planar configuration of the trenchisolation structures 911, the P type semiconductor regions 912 and the Ntype semiconductor regions 913, in reference to FIGS. 5 through 11.FIGS. 5, 8 through 11 are plane views illustrating the semiconductordevice 100 in a semiconductor chip state seen from the side of thesecond main surface MS2.

FIG. 5 illustrates an example where a plurality of the loop trenchisolation structures 911 having a rectangular outline are disposed inparallel with an interval. The N type semiconductor regions 913 aredisposed in a region surrounded by the loop trench isolation structure911. The P type semiconductor region 912 is disposed surrounding thetrench isolation structures 911.

FIGS. 6 and 7 show an example of a planar configuration of the trenches903 seen from the side of the first main surface MS1. In an exampleshown in FIG. 6, a plurality of striped trenches 903 are disposed inparallel with an interval in the surface of the P type semiconductorregion 902. The arranging direction of the trenches 903 corresponds tothe arranging direction of the trench isolation structures 911.

Further, an example shown in FIG. 7 also shows a plurality of stripedtrenches 903 disposed in parallel with an interval in the surface of theP type semiconductor region 902. However, the arranging direction of thetrenches 903 is at right angle to the arranging direction of the trenchisolation structures 911. It is noted that FIGS. 6 and 7 do not show theN type semiconductor regions 906 and the like for convenience. Thisarrangement of the trenches 903 and the trench isolation structures 911with respective arranging directions forming a right angle produces anadvantage that a uniform current distribution can be made.

FIG. 8 shows an example where a plurality of the loop trench isolationstructures 911 having a rectangular outline are concentrically arrangedwith an interval. In this configuration, the loop formed by theinnermost trench isolation structure 911 is the smallest, and the loopbecomes larger as a location of respective trench isolation structures911 moves outwardly. The P type semiconductor region 912 is provided inthe region surrounded by the innermost trench isolation structure 911,and the N type semiconductor region 913 is provided surrounding theinnermost trench isolation structure 911. In a similar manner, the Ptype semiconductor regions 912 and the N type semiconductor regions 913are provided alternately to surround each of the trench isolationstructures 911.

FIG. 9 shows an example where a plurality of the striped trenchisolation structures 911 are provided in parallel with an interval. TheP type semiconductor regions 912 and the N type semiconductor regions913 are provided alternately between the plurality of the trenchisolation structures 911. This alternate arrangement of the P typesemiconductor regions 912 and the N type semiconductor regions 913 isemployed at a central portion of the trench isolation structures 911.Both ends of the trench isolation structures 911 are formed inside thesurface of the semiconductor substrate 901 with a low impurityconcentration, and the P type semiconductor region 912 is provided atthe periphery of a semiconductor chip.

FIG. 10 shows an example where a plurality of the loop trench isolationstructures 911 having a rectangular outline (small loop) are provided inparallel with an interval, while a larger loop trench isolationstructure 911 having a rectangular outline (large loop) is provided soas to surround the small loop arrangement. The N type semiconductorregions 913 are provided inside the small loop trench isolationstructures 911, while the P type semiconductor region 912 is providedsurrounding the small loop trench isolation structure 911. Further, theN type semiconductor region 913 is provided surrounding the large looptrench isolation structure 911.

FIG. 11 shows an example where a plurality of the striped trenchisolation structures 911 are provided in parallel with an interval. TheP type semiconductor regions 912 and the N type semiconductor regions913 are provided alternately between the plurality of the trenchisolation structures 911. In this example, the trench isolationstructures 911 are extended to reach the edge of a semiconductor chip.The P type semiconductor regions 912 and the N type semiconductorregions 913 are separated from each other by the trench isolationstructures 911 and the chip edge.

FIG. 12 shows a planer structure of a semiconductor wafer to obtainsemiconductor chips as shown in FIGS. 5 through 11. On a semiconductorwafer WF of FIG. 12, a plurality of the striped trench isolationstructures 911 are provided. Dicing lines DL are provided horizontallyand vertically for dividing the semiconductor wafer WF into a pluralityof semiconductor chips.

B. Operation

Next, description is given of an operation of the semiconductor device100 in reference to FIGS. 13 and 14. FIG. 13 is an equivalent circuitschematically illustrating function of the semiconductor device 100,showing that the semiconductor device 100 functions as an IGBT elementand a diode element in an inverse-parallel connection with the IGBTelement. Further, FIG. 14 shows current-voltage characteristics of thesemiconductor device 100.

FIG. 13 shows that the trench isolation structure 911 is provided in thesurface of the semiconductor substrate 901 between the P typesemiconductor region 912 and the N type semiconductor region 913. Underthis configuration, when a ground potential is supplied to the externalterminal ET, a positive potential is supplied to the external terminalCT and an ON signal is supplied to the external terminal GT, the currentpath (1) and the current path (2) are formed leading to the first mainsurface MS1 side. The current path (1) starts from the N typesemiconductor region 913, goes through a path having resistors R11, R1and R12 inside the semiconductor substrate 901 and a channel regionformed inside the P type semiconductor region 902 in contact with thegate insulating film 904, and reaches the N type semiconductor region906. The current path (2) starts from the P type semiconductor region912, goes through a path having resistors R13 and R12 inside thesemiconductor substrate 901 and the channel region formed inside the Ptype semiconductor region 902 in contact with the gate insulating film904, and reaches the N type semiconductor region 906.

In this case, the current path (1) is taken during an operation as aso-called MOSFET element, and the current path (2) is taken during anoperation as a so-called IGBT element.

Further, when a ground potential is supplied with the external terminalET, a negative potential is supplied to the external terminal CT and anOFF signal is supplied to the external terminal GT, the semiconductordevice 100 functions as a diode element. Then a current path (3) isformed going through a path with a resistor R14 inside the semiconductorsubstrate 901 and reaching the N type semiconductor region 913.

A point where a current generated when the semiconductor device 100operates as an IGBT element and a current generated when thesemiconductor device 100 operates as a MOSFET element meet is hereinreferred to as an X1. Because the P type semiconductor region 912 andthe N type semiconductor region 913 are separated by the trenchisolation structure 911, the resistor R13 is present between the P typesemiconductor region 912 and the X1 while the resistors R11 and R1 arepresent between the N type semiconductor region 913 and the X1.Therefore, it is possible to increase a resistance value between theexternal terminal CT and the X1, thereby easily increasing a potentialdifference between the external terminal CT and the X1. It is noted thatwhile the resistor R1 exhibits a small resistance value, as in the caseof the semiconductor device 90 shown in FIG. 2, the resistor R11exhibits a considerably larger resistance value in comparison to theresistor R1.

Additionally in FIG. 13, regarding the resistors R12 and R13 inside thesemiconductor substrate 901 when the semiconductor substrate 100functions as an IGBT element, and regarding the resistor R14 when thesemiconductor substrate 100 functions as a diode element, modulation isgenerated and a resistance value decreases as a voltage increases.Accordingly, a symbol indicating a variable resistor is used for theresistors R12 and R13. However, in case of a MOSFET element operation,the resistance value is approximately constant.

FIG. 14 conceptually shows current-voltage characteristics of thesemiconductor device 100. That is, in FIG. 14, the horizontal axisrepresents voltage value and the vertical axis represents current value,to indicate four kinds of current-voltage characteristics that arecharacteristics A1, B1, C1 and D1. For comparison, characteristics A, B,C and D shown in FIG. 2 are also indicated.

The characteristic A1 shows the relationship of a current flowing at theexternal terminal CT and a potential difference between the externalterminal CT and the X1 when the N type semiconductor region 913 is in anopen state without being connected to the external terminal CT.

The characteristic B1 shows the relationship of a current flowing at theexternal terminal CT and a potential difference between the externalterminal CT and the X1 when the P type semiconductor region 912 is in anopen state without being connected to the external terminal CT.

The characteristic C1 shows the relationship of a current flowing at theexternal terminal CT and a potential difference between the externalterminal CT and the external terminal ET when the N type semiconductorregion 913 is in an open state without being connected to the externalterminal CT.

The characteristic D1 shows the relationship of a current flowing at theexternal terminal CT and a potential difference between the externalterminal CT and the external terminal ET when the P type semiconductorregion 912 is in an open state without being connected to the externalterminal CT.

Further, a characteristic A′ shows a relationship of a current flowingat the external terminal CT and a potential difference between theexternal terminal CT and an X′ when the N type semiconductor region 913is in an open state without being connected to the external terminal CT.

The area of the P type semiconductor region 912 and the area of the Ntype semiconductor region 913 are both set in the same manner as for thesemiconductor device 90 in FIG. 2. Therefore, the characteristics C1 andD1 are the same as the characteristics C and D shown in FIG. 3,respectively.

In contrast, a larger distance between the X1 and the N typesemiconductor region 913 results in a larger resistance valuetherebetween (the sum of resistance values of the resistors R1 and R11),and the characteristic B1 shows a considerably gradual slope compared tothe characteristic B.

As a result, even when a potential difference between the externalterminal CT and the X1 reaches about 0.6 V and reaches a modulationvoltage Vmod where modulation starts to be generated (a voltageindicated by the Z), almost no current flows and a voltage differencebetween the external terminal CT and the external terminal ET is small,thereby suppressing snapback. Here, a current ic flowing at the resistorR13 is almost 0 and the following relationship holds at the Z:Vmod=(R11+R1)×id. Since the resistor (R11+R1) has a large resistancevalue, the small current id can turn on a collector of the IGBT. The idhere refers to an operating current of the MOSFET element, that is, acurrent flowing through the current path (1). In this case, itparticularly refers to a current value at the Z. The current ic refersto an operating current of the IGBT element, that is, a current flowingthrough the current path (2) and equals to 0 at the Z.

As described above, snapback can be suppressed in the semiconductordevice 100 and it is not necessary to reduce the proportion of an areaof an effective region (the sum of areas of the P type semiconductorregion 912 and the N type semiconductor region 913) in the second mainsurface MS2. Therefore, increase of an ON voltage at an IGBT elementoperation and a forward voltage Vf at a diode element operation as wellas increase of a local current density at respective operations isprevented.

C. Manufacturing Method

Next, description is given of a manufacturing method of thesemiconductor device 100 in reference to FIGS. 15 through 18. Thestructure on the side of the first main surface MS1 is obtained throughthe same manufacturing processes employed for IGBTs and MOSFETsconventionally known to the public. Therefore, description regarding theknown technique is omitted.

FIGS. 15 through 18 are section views sequentially illustratingmanufacturing steps for obtaining the structure on the side of thesecond main surface MS2. In the following description, it is assumedthat the structure below the first main electrodes 908 on the first mainsurface MS1 side has been already formed.

After forming the structure below the first main electrodes 908 (thestructure being not shown) on the side of the first main surface MS1 ofthe semiconductor substrate 901, in the process shown in FIG. 15,trenches TR are formed in the second main surface MS2 of thesemiconductor substrate 901 using photo lithography and anisotropicetching.

Here, a thickness T of the semiconductor substrate 901 is set to athickness that hardly causes a crack or a chip on a semiconductor waferduring manufacturing process of a semiconductor device. Also, thethickness T is set to a thickness that does not require specialadjustments in focal depth in an aligner and the like during the photolithography process. Taking a 6-inch semiconductor wafer as an example,the thickness is set to between 500 to 650 μm. Further, a thickness Sfrom the bottom of the trenches TR to the first main surface MS1 isdetermined in consideration of a reduction in an ON resistance and awithstand voltage. For example, for a semiconductor device with awithstand voltage of 600V, the thickness is set to 60 μm.

Additionally, any value can be given for a width and an arrangementinterval of the trenches TR. For example, the width is set to 0.2 to 100μm and the arrangement interval is set to 0.5 to 500 μm.

Next, in the step shown in FIG. 16, an insulating film ZL with athickness greater than the width of the trench TR is deposited by a CVDmethod and the like on the entire second main surface MS2, therebyfilling the insulating film ZL inside the trenches TR.

Then, in the step shown in FIG. 17, etch back is performed byanisotropic etching and the like to remove the insulating film ZL on thesecond main surface MS2, thereby obtaining the trench isolationstructures 911 comprising the insulators 914.

In case it is necessary to obtain a desirable property, in the stepshown in FIG. 18, the second main surface MS2 side may be polished byanisotropic etching or a polishing method such as CMP (ChemicalMechanical Polishing), thereby obtaining a desirable substratethickness. Naturally in this case, the relationship between a substratethickness M after polishing, the thickness T and the thickness S isS<M<T.

Generally, the P type semiconductor regions 912 and the N typesemiconductor regions 913 are formed before the trench isolationstructures 911, and the trench isolation structures 911 is formed at theboundary between the P type semiconductor regions 912 and the N typesemiconductor regions 913. In case a polishing mentioned in reference toFIG. 18 is performed, the P type semiconductor regions 912 and the Ntype semiconductor regions 913 are formed after the polishing.

Thereafter, a conductive material constituting the second main electrode916 is deposited by an evaporation method and the like to obtain thestructure on the side of the second main surface MS2.

The foregoing description specifies that the structure of the secondmain surface MS2 side is formed after the structure of the first mainsurface MS1 side is formed. However, this does not limit the formationof the structure of the second main surface MS2 side. Unless thetrenches TR cause an adverse effect in the formation of the structure ofthe first main surface MS1 side, the structure of the second mainsurface MS2 side may be formed while forming the structure of the firstmain surface MS1 side.

Further, since it is desirable that the P type semiconductor regions 912and the N type semiconductor regions 913 are fully activated byannealing, it is desirable that an annealing process is carried outafter the formation of the P type semiconductor regions 912 and the Ntype semiconductor regions 913.

Moreover, timing to form the second main electrode 916 is not limited tothe above description. Nevertheless, since a multilayered metal filmstructure including gold and silver is employed, it is desirable thatthe second main electrode 916 is formed in the final step of waferprocessing.

D. Variation

In the above-described example of the semiconductor device 100, thesemiconductor substrate 901 comprises an N type semiconductor substrate.Naturally, the same effect is also achieved when the semiconductorsubstrate 901 comprises a P type semiconductor substrate.

Further, the semiconductor device 100 has the configuration wherein theP type semiconductor regions 912 and the N type semiconductor regions913 are both connected to the second main electrode 916 which coversboth the P type semiconductor regions 912 and the N type semiconductorregions 913. This configuration is simple and does not require complexwiring and the like for connecting to the external terminal CT. In thisregard, as shown in FIG. 19, a semiconductor device 100A presentsanother possible configuration wherein second main electrodes 916 aconnected to the P type semiconductor regions 912 and second mainelectrodes 916 b connected to the N type semiconductor regions 913 areprovided so that the P type semiconductor regions 912 and the N typesemiconductor regions 913 respectively are connected to a separate mainelectrode.

In this case, since the second main electrodes 916 b are connected tothe external terminal CT via a resistor element 915, a resistance insidethe semiconductor substrate 901 between the N type semiconductor regions913 and the P type semiconductor regions 912 needs to be smaller thanthat of the semiconductor device 100. Therefore, the depth of trenchisolation structures 911 can be reduced. It is noted that the secondmain electrodes 916 a may be connected to a diode element or atransistor element as a current limiter in place of the resistor element915. In this manner, the configuration of the P type semiconductorregions 912 and the N type semiconductor regions 913 being connected toa separate main electrode allows various structures to be applied.

Further, as in the case of the semiconductor device 100 wherein thesecond main electrode 916 covers both the P type semiconductor regions912 and the N type semiconductor regions 913, by selecting a material ofthe second main electrode 916 so that a contact resistance to the N typesemiconductor regions 913 is greater than a contact resistance to the Ptype semiconductor regions 912, the same advantageous effect derivedfrom the semiconductor device 100A shown in FIG. 19 can be achieved. Forexample, a metal with a large work function such as gold and silver canbe used.

Also, the embodiment described an example wherein the trench isolationstructures 911 are formed by filling the insulators in the trenches. Inanother possible configuration, the trench isolation structures may beformed by filling a high-resistance semiconductor of a conductivity typereverse to that of the semiconductor substrate 901 with an impurityconcentration approximately equal to that of the semiconductor substrate901 (for example, for an element with a withstand voltage of 1200V, animpurity concentration being 1×10¹⁴ atoms/cm³, a specific resistancebeing 50 to 60 ohms).

In case the trench isolation structures 911 are formed with ahigh-resistance semiconductor, an insulating film may be formed betweenthe high-resistance semiconductor, the N type semiconductor regions 913and the P type semiconductor regions 912. The above insulating film mayor may not be formed at the bottom of the trench isolation structures911.

Furthermore, the trench isolation structures 911 may consist of trenchesalone, without filling an insulating material or a high-resistancesemiconductor material inside the trenches TR.

Additionally, the application of the present invention is not limitedonly to an IGBT element and a diode element, and application to athyristor element is also possible.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

1. A semiconductor, comprising: a first main electrode provided on afirst main surface of a semiconductor substrate; a second main electrodeprovided on a second main surface of said semiconductor substrateopposite to the first main surface in a direction of the thickness ofsaid semiconductor, and configured to allow a main current to flow inthe direction of the thickness of said semiconductor substrate; and atleast one trench-type gate electrode provided in said first mainsurface, said semiconductor substrate comprising at least one trenchisolation structure provided in said second main surface, and a firstimpurity region of a first conductivity type and a second impurityregion of a second conductivity type provided in said second mainsurface, wherein said at least one trench isolation structure includes atrench in said second main surface filled with an insulator or asemiconductor of a conductivity type reverse to that of saidsemiconductor substrate, said at least one trench isolation structureconfigured to separate said first impurity region and said secondimpurity region, wherein an exposed surface of said at least one trenchisolation structure provided in the portion of said second main surfaceis level with an exposed surface of said first and second impurityregions, and said second main electrode covers said at least one trenchisolation structure and said first and second impurity regions and iselectrically commonly connected to them.
 2. The semiconductor accordingto claim 1, wherein said at least one trench isolation structure isconfigured such that an electrical charge inside said insulator has apolarity reverse to an electrical charge inside said semiconductorsubstrate and a total quantity of the electrical charge of said at leastone trench isolation structure is approximately equal to a quantity ofthe electrical charge of a section of said semiconductor substrate fromsaid second main surface to the bottom of said at least one trenchisolation structure.
 3. The semiconductor according to claim 1, whereina width of said at least one trench isolation structure is set to avalue in a range between 0.2 to 100 μm and an arrangement interval isset to a value in a range between 0.5 to 500 μm.